pcie

Description

The pcie plugin reads and writes data from/to the PCIe bus. There are two available plugins: pciesocsrc and pciesocsink that runs on the SiMa MLSoC.

Features

simaaipciesrc

Multiple source pad/stream support

simaaipciesrc provides a capability to link more than 1 downstream elements by using GST_PAD_REQUEST in its source pad template. Each source pad must have an associated sink pad on host side. Once new source pad is created it receives its id which is number representing the order this pad was created: 0, 1, 2… Each buffer that comes from host has a stream-id field which has a similar value. This value is being evaluated against source pads ids. Once it is matched - data buffer will pushed to this pad. For example: buffer with stream-id=2 will be pushed to src_2. Count starts from 0.

CAPs Negotiation

Negotiation happens between PCIe Host sink pad and associated simaaipciesrc source pad. The flow as follows: - All sink pads of host element receives GST_EVENT_CAPS - GstCaps values are combined into one single message and passed to SoC - simaaipciesrc receives message, checks the no:of caps with no:of src pads available. If this check passes - assigns caps from host to associated src pad - simaaipciesrc sends GST_EVENT_CAPS to each src pad peer and performs CAPs negotiation.

Automatic Output Buffer Size Calculation

simaaipciesrc can automatically calculate output buffer size from the negotiated CAPs by using the following formula:

image_width * image_height * stride. That means CAPs shall contain information about frame width and height and format. Format is used to deduce stride parameter. Currently, simaaipciesrc plugin can automatically deduce stride for the following formats: - NV12 - I420 - RGB - BGR
If the format differs from those listed above, the user can specify output buffer size manually, by using the buffer-size property. Otherwise, the default buffer size value (4MB) will be used.

simaaipciesink

Supports one sink pad
Allows any CAPs from upstream element

Getting Started

These plugins are part of the Board Support Package (BSP). That means, the user will not need to build them manually, they are available out-of-box on the board.

To build the plugin use:

source /opt/poky/4.0.10/environment-setup-cortexa65-poky-linux mkdir build && cd build && cmake -DBSP_PLUGINS=ON .. && make

Also, the user will need to install the PCIe host package on the host x86 machine which contains pciehost GStreamer, plugin, PCIe driver and host library, see Installation section.

Prerequisites

Yocto SDK must be installed on the board.

Installation

SoC

scp libgstpciesocsink.so libgstpciesrc.so sima@<IP address of DaVinci board>:/data/my_pipeline/libs

Host Machine

curl -O soc-images/1.5.0_custom_develop_B3311/artifacts/host_files/sima_pcie_host_pkg.sh

chmod +x sima_pcie_host_pkg.sh

./sima_pcie_host_pkg.sh

Example Usage

SoC:

GST_DEBUG=2 gst-launch-1.0 simaaipciesrc ! simaaipciesink

Host:

GST_DEBUG=0 gst-launch-1.0 rtspsrc location=<RTSP_SRC> ! rtph264depay ! h264parse ! avdec_h264 ! videoconvert ! video/x-raw,format=I420 ! pciehost queuedepth=8 fps=30 ! videoparse format=i420 width=1280 height=720 ! autovideoconvert ! autovideosink

Configuration

No configuration needed for these plugins. Please use to gst-inspect-1.0 to get actual list of properties, available for these plugins.